1. Field of the Invention
The present invention is directed to the manufacture of masks used in the lithographic production of integrated circuits and, in particular, to the manufacture of masks for improved gate dimensional control.
2. Description of Related Art
Variations in local pattern density are known to affect the final dimension of critical semiconductor features, including polysilicon gates. One important mechanism connecting pattern density and gate critical dimension is optical flare, wherein the photoresist dimension of a critical gate feature is impacted by a paucity of scattered light from nearby dark features on the photomask reticle. For advanced technologies with very fine gate features, the linewidth variations associated with locally-low optical flare conditions can have profound a effect on the operating frequency and the power draw of the final device.
A well-know solution to this problem is a set of layout constraints that constrain the maximum local density of gate features. These constraints may apply across the entire design, or only in the immediate vicinity of critical gates. Density-related layout constraints drive longer design cycles and larger chips. Locally high-density regions in a copper wiring layout are sometimes accommodated by the automatic placement of clear openings in the interior of wide copper features, which openings transmit light images corresponding to their shapes. Since these clear openings are resolved in the resist layer on the wafer, and result in the final device as gaps in the copper feature, this approach is not appropriate for gate features that would not function appropriately with a perforated interior.